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CAT24C256 Datasheet(PDF) 6 Page - Catalyst Semiconductor

No. de Pieza. CAT24C256
Descripción  256-Kb I2C CMOS Serial EEPROM
Descarga  14 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
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CAT24C256 Datasheet(HTML) 6 Page - Catalyst Semiconductor

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Doc. No. 04, Rev. D
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be
written (Figure 5). The Slave acknowledges all 4 bytes,
and the Master then follows up with a STOP, which in
turn starts the internal Write operation (Figure 6). During
internal Write, the Slave will not acknowledge any Read
or Write request from the Master.
Page Write
in 52 pages of 64 bytes each.Atwo byte address word,
following the Slave address, points to the first byte to be
written. The most significant bit of the address word is
‘don’t care’, the next 9 bits identify the page and the last
6 bits identify the byte within the page. Up to 64 bytes
can be written in one Write cycle (Figure 7).
The internal byte address counter is automatically in-
cremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page).The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C256 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is pro-
tected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation
of the CAT24C256.

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