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CAT24C0A1UTE13 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT24C0A1UTE13 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 8 page Discontinued Part CAT24C01B 5 Doc. No. 1081, Rev. E © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24C01B monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg- ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24C01B responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When the CAT24C01B is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowl- edge, the CAT24C01B will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C01B. After receiving another acknowl- edge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24C01B acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24C01B writes up to 4 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 3 additional bytes. After each byte has been transmitted the CAT24C01B will respond with an ac- knowledge, and internally increment the low order ad- dress bits by one. The high order bits remain un- changed. If the Master transmits more than 4 bytes prior to sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. Once all 4 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24C01B in a single write cycle. Note: Catalyst Semiconductor does program all "1" data into the entire memory array prior to shipping our EEPROM products. Figure 4. Acknowledge Timing 5020 FHD F06 ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER |
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