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CAT24WC128_05 Datasheet(Hoja de datos) 3 Page - Catalyst Semiconductor

No. de Pieza. CAT24WC128_05
Descripción  128K-Bit I2C Serial CMOS EEPROM
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT24WC128
3
Doc. No. 1038, Rev. E
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
Power-Up Timing (1)(2)
Symbol
Parameter
Max.
Units
tPUR
Power-Up to Read Operation
1
ms
tPUW
Power-Up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
FUNCTIONAL DESCRIPTION
The CAT24WC128 supports the I2C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min.
Max.
Min.
Max.
Min.
Max.
Units
FSCL
Clock Frequency
100
400
1000
kHz
tAA
SCL Low to SDA Data Out
0.1
3.5
0.05
0.9
0.05
0.55
µs
and ACK Out
tBUF(1)
Time the Bus Must be Free Before
4.7
1.2
0.5
µs
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
4.0
0.6
0.25
µs
tLOW
Clock Low Period
4.7
1.2
0.6
µs
tHIGH
Clock High Period
4.0
0.6
0.4
µs
tSU:STA
Start Condition Setup Time
4.0
0.6
0.25
µs
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
0
0
ns
tSU:DAT
Data In Setup Time
100
100
100
ns
tR(1)
SDA and SCL Rise Time
1.0
0.3
0.3
µs
tF(1)
SDA and SCL Fall Time
300
300
100
ns
tSU:STO
Stop Condition Setup Time
4.7
0.6
0.25
µs
tDH
Data Out Hold Time
100
50
50
ns
tWR
Write Cycle Time
10
10
10
ms
STOP conditions for bus access. The CAT24WC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.




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