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CAT25C08_06 Datasheet(Hoja de datos) 6 Page - Catalyst Semiconductor

No. de Pieza. CAT25C08_06
Descripción  8K/16K SPI Serial CMOS EEPROM
Descarga  16 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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6
CAT25C08/16
Doc. No. 1016, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 2. WREN Instruction Timing
Figure 3. WRDI Instruction Timing
Note: Dashed Line= mode (1, 1) – ––––
SCK
SI
CS
SO
00000
11
0
HIGH IMPEDANCE
SCK
SI
CS
SO
00000
10
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – ––––
STATUS REGISTER
The Status Register indicates the status of the device.
The
RDY (Ready) bit indicates whether the CAT25C08/
16 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only. The WEL
(Write Enable) bit indicates the status of the write
enable latch. When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state.
The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for
the
WP pin. The WP pin and WPEN bit in the status
register control the programmable hardware write pro-
tect feature. Hardware write protection is enabled when
WP is low and WPEN bit is set to high. The user cannot
write to the status register, (including the block protect
WP
WP
WP
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP going low will
have no effect on any write operation to the status
register. The
WP pin function is blocked when the WPEN
bit is set to 0.
Figure 10 illustrates the
WP timing
sequence during a write operation.
HOLD
HOLD
HOLD
HOLD
HOLD: Hold
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C08/16 while in the middle of
a serial sequence without having to re-transmit entire
sequence at a later time. To pause,
HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,
HOLD is brought high, while SCK is low.
HOLD should be held high any time this function is not
being used.
HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.




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