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CAT25C08 Datasheet(PDF) 8 Page - Catalyst Semiconductor

No. de Pieza. CAT25C08
Descripción  8K/16K SPI Serial CMOS EEPROM
Descarga  16 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT25C08 Datasheet(HTML) 8 Page - Catalyst Semiconductor

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8
CAT25C08/16
Doc. No. 1016, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SCK
SI
SO
00
00
00
10
D7
D6
D5
D4
D3
D2
D1
D0
012345678
21
22
23
24
25
26
27
28
29
30
31
CS
OPCODE
*Please check the Byte Address Table
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
*
AN
A0
Figure 6. Write Instruction Timing
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits). Programming will
start after the
CS is brought high. Figure 6 illustrates
byte write sequence. During an internal write cycle, all
commands will be ignored except the RDSR (Read
Status Register) instruction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C08/16 features page write capability. After
the initial byte, the host may continue to write up to 32
Note: Dashed Line= mode (1, 1) – ––––
bytes. After each byte of data received, lower order
address bits are internally incremented by one; the high
order bits of address will remain constant.The only
restriction is that the 32 bytes must reside on the same
page. If the address counter reaches the end of the
page and clock continues, the counter will “roll over” to
the first address of the page and overwrite any data that
may have been written. The CAT25C08/16 is automati-
cally returned to the write disable state at the completion
of the write cycle. Figure 8 illustrates the page write
sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 5. RDSR Instruction Timing
Note: Dashed Line= mode (1, 1) – ––––
0
1
2
345
67
8
10
911
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
00
0
00
1
0
1


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