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CAT25C09PITE13 Datasheet(Hoja de datos) 4 Page - Catalyst Semiconductor

No. de Pieza. CAT25C09PITE13
Descripción  1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
Descarga  12 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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Discontinued
Parts
4
CAT25C11/03/05/09/17
Doc. No. 1017, Rev. L
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DESCRIPTION
The CAT25C11/03/05/09/17 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C11/03/05/09/17 to
interface directly with many of today’s popular
microcontrollers. The CAT25C11/03/05/09/17 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
After the device is selected with
CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 X011(1)
Read Data from Memory
WRITE
0000 X010(1)
Write Data to Memory
INSTRUCTION SET
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C11/03/05/09/17.Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the 25C11/03/05/09/17. During a read cycle,
data is shifted out on the falling edge of the serial clock for
Figure 1. Sychronous Data Timing
CS
NC
1
2
3
4
14
13
12
11
NC
NC
NC
5
6
710
9
8
NC
SCK
VSS
SI
NC
WP
VCC
HOLD
SO
15
16
NC
NC
Note: Dashed Line= mode (1, 1) – – – –
Note:
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Power-Up Timing(2)(3)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms




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