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CAT25C33_05 Datasheet(Hoja de datos) 5 Page - Catalyst Semiconductor

No. de Pieza. CAT25C33_05
Descripción  32K/64K-Bit SPI Serial CMOS EEPROM
Descarga  11 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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 5 page
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Discontinued
Parts
5
CAT25C33/65
Doc No. 1000, Rev. H
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C33/65. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
CS
CS
CS
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C33/
65 and
CS high disables the CAT25C33/65. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C33/65 draws
ZERO current in the Standby mode. A high to low
transition on
CS is required prior to any sequence being
initiated. A low to high transition on
CS after a valid write
sequence is what initiates an internal write cycle.
WP
WP
WP
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When
WP is
tied low and the WPEN bit in the status register is set to “1”,
all write operations to the status register are inhibited.
WP
going low while
CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to the
status register. The
WP pin function is blocked when the
WPEN bit is set to 0.
HOLD
HOLD
HOLD
HOLD
HOLD: Hold
The
HOLD pin is used to pause transmission to the
CAT25C33/65 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later time.
To pause,
HOLD must be brought low while SCK is low. The
SO
pin
is
in
a
high
impedance
state
during
the time the part is paused, and transitions on the SI pins
will be ignored. To resume communication,
HOLD is brought
high, while SCK is low.
(HOLD should be held high any time
this function is not being used.)
HOLD may be tied high
Protected
Unprotected
Status
WPEN
WP
WP
WP
WP
WP
WEL
Blocks
Blocks
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
WRITE PROTECT ENABLE OPERATION
76543210
WPEN
X
X
BP2
BP1
BP0
WEL
RDY
STATUS REGISTER
BP2
BP1
BP0
0
0
0
Non-Protection
0
0
1
Q1 Protected
0
1
0
Q2 Protected
0
1
1
Q3 Protected
1
0
0
Q4 Protected
1
0
1
H1 Protected
1
1
0
P0 Protected
1
1
1
Pn Protected
MEMORY PROTECTION
CAT25C33
CAT25C65
Q1
0000-03FF
0000-07FF
Q2
0400-07FF
0800-0FFF
Q3
0800-0BFF
1000-17FF
Q4
0C00-0FFF
1800-1FFF
H1
0000-07FF
0000-0FFF
P0
0000-003F
0000-003F
Pn
0FC0-0FFF
0FC0-1FFF
MEMORY PROTECTION




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