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CAT25C33 Datasheet(PDF) 7 Page - Catalyst Semiconductor

No. de Pieza. CAT25C33
Descripción  32K/64K-Bit SPI Serial CMOS EEPROM
Descarga  11 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT25C33 Datasheet(HTML) 7 Page - Catalyst Semiconductor

 
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Discontinued
Parts
7
CAT25C33/65
Doc No. 1000, Rev. H
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 4. Read Instruction Timing
Figure 5. RDSR Instruction Timing
Note: Dashed Line= mode (1, 1) — — — —
Note: Dashed Line= mode (1, 1) — — — —
SK
SI
SO
0000001
1
BYTE ADDRESS*
0123456789
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
CS
OPCODE
DATA OUT
MSB
HIGH IMPEDANCE
0
1
2
345
67
8
10
911
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
00
0
00
1
0
1
up in a write disable state when Vcc is applied. WREN
instruction will enable writes (set the latch) to the device.
WRDI instruction will disable writes (reset the latch) to
the device.
Disabling writes will protect the device
against inadvertent writes.
READ Sequence
The part is selected by pulling
CS low. The 8-bit read
instruction is transmitted to the CAT25C33/65, followed
by the 16-bit address(the three Most Significant Bits are
don’t care for 25C65 and four most significant bits are
don't care for 25C33). After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address (1FFFh for 25C65
and FFFh for 25C33) is reached, the address counter rolls
over to 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by pulling the
CS high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be read
at any time even during a write cycle. Read sequece is
illustrated in Figure 4. Reading status register is illustrated
in Figure 5.
WRITE Sequence
The CAT25C33/65 powers up in a Write Disable state. Prior
to any write instructions, the WREN instruction must be
sent to CAT25C33/65. The device goes into Write enable
state by pulling the
CS low and then clocking the WREN
instruction into CAT25C33/65. The
CS must be brought
high after the WREN instruction to enable writes to the
device.


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