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CAT25C33 Datasheet(PDF) 9 Page - Catalyst Semiconductor

No. de Pieza. CAT25C33
Descripción  32K/64K-Bit SPI Serial CMOS EEPROM
Descarga  11 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT25C33 Datasheet(HTML) 9 Page - Catalyst Semiconductor

 
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Discontinued
Parts
9
CAT25C33/65
Doc No. 1000, Rev. H
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 9.
HOLD
HOLD
HOLD
HOLD
HOLD Timing
DESIGN CONSIDERATIONS
Figure 8. Page Write Instruction Timing
The CAT25C33/65 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up
CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C33/65 goes into a write disable mode.
CS must
be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and program-ming
is continued. On power up, SO is in a high impedance.
Note: Dashed Line = mode (1, 1) – – – –
Note: Dashed Line= mode (1, 1) — — — —
SK
SI
SO
0
0
0
0
0
0
1
0
ADDRESS
Data
Byte 1
012345678
21
22
23 24-31
32-39
Data
Byte 2
Data
Byte 3
Data Byte N
CS
OPCODE
7..1
0
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
DATA IN
HIGH IMPEDANCE
CS
SCK
HOLD
SO
tCD
tHD
tHD
tCD
tLZ
tHZ
HIGH IMPEDANCE
When powering down, the supply should be taken down
to 0V, so that the CAT25C33/65 will be reset when power
is ramped back up. If this is not possible, then, following
a brown-out episode, the CAT25C33/65 can be reset by
refreshing the contents of the Status Register (See Appli-
cation Note AN10).


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