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CAT28F001 Datasheet(PDF) 5 Page - Catalyst Semiconductor

No. de Pieza. CAT28F001
Descripción  1 Megabit CMOS Boot Block Flash Memory
Descarga  18 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT28F001 Datasheet(HTML) 5 Page - Catalyst Semiconductor

 
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CAT28F001
5
Doc. No. 1078, Rev. I
SUPPLY CHARACTERISTICS
Limits
Symbol
Parameter
Min
Max.
Unit
VLKO
VCC Erase/Write Lock Voltage
2.5
V
VCC
VCC Supply Voltage
4.5
5.5
V
VPPL
VPP During Read Operations
0
6.5
V
VPPH
VPP During Erase/Program
11.4
12.6
V
VHH
RP, OE Unlock Voltage
11.4
12.6
V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
(2)
Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3)
Input Rise and Fall Times (10% to 90%) < 10 ns.
(4)
Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5)
Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6)
Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7)
For load and reference points, see Fig. 1
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.8 V
VCC - 0.3V
0.0 V
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
Testing Load Circuit (example)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
INPUT PULSE LEVELS
REFERENCE POINTS
3.0 V
0.0 V
1.5 V
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
Testing Load Circuit (example)
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