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CAT25C08LE-1.8-GT3 Datasheet(Hoja de datos) 5 Page - Catalyst Semiconductor

No. de Pieza. CAT25C08LE-1.8-GT3
Descripción  8K/16K SPI Serial CMOS EEPROM
Descarga  16 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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5
CAT25C08/16
Doc. No. 1016, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Status Register Bits
Array Address
Protection
BP1
BP0
Protected
0
0
None
No Protection
0
1
25C08: 0300-03FF
Quarter Array Protection
25C16: 0600-07FF
1
0
25C08: 0200-03FF
Half Array Protection
25C16: 0400-07FF
1
1
25C08: 0000-03FF
Full Array Protection
25C16: 0000-07FF
BLOCK PROTECTION BITS
76543210
WPEN
0
1
0
BP1
BP0
WEL
RDY
STATUS REGISTER
Protected
Unprotected
Status
WPEN
WP
WP
WP
WP
WP
WEL
Blocks
Blocks
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
WRITE PROTECT ENABLE OPERATION
and the 25C08/16. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS
CS
CS
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C08/
16 and
CS high disables the CAT25C08/16. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway) The CAT25C08/16 draws
ZERO current in the Standby mode. A high to low
transition on
CS is required prior to any sequence being
initiated. A low to high transition on
CS after a valid write
sequence is what initiates an internal write cycle.
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25C08
A9 - A0
A15 - A10
16
CAT25C16
A10 - A0
A15 - A11
16




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