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CAT28F020 Datasheet(PDF) 1 Page - Catalyst Semiconductor

No. de Pieza. CAT28F020
Descripción  2 Megabit CMOS Flash Memory
Descarga  15 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT28F020 Datasheet(HTML) 1 Page - Catalyst Semiconductor

 
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1
I/O0–I/O7
I/O BUFFERS
CE, OE LOGIC
SENSE
AMP
DATA
LATCH
ERASE VOLTAGE
SWITCH
PROGRAM VOLTAGE
SWITCH
COMMAND
REGISTER
CE
OE
WE
VOLTAGE VERIFY
SWITCH
Y-DECODER
X-DECODER
Y-GATING
2,097,152 BIT
MEMORY
ARRAY
A0–A17
CAT28F020
2 Megabit CMOS Flash Memory
Licensed Intel second source
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FEATURES
I Fast read access time: 90/120 ns
I Low power CMOS dissipation:
– Active: 30 mA max (CMOS/TTL levels)
– Standby: 1 mA max (TTL levels)
– Standby: 100
µA max (CMOS levels)
I High speed programming:
– 10
µs per byte
– 4 seconds typical chip program
I 0.5 seconds typical chip-erase
I 12.0V
± 5% programming and erase voltage
I Commercial, industrial and automotive
temperature ranges
I Stop timer for program/erase
I On-chip address and data latches
I JEDEC standard pinouts:
– 32-pin DIP
– 32-pin PLCC
– 32-pin TSOP (8 x 20)
I 100,000 program/erase cycles
I 10 year data retention
I Electronic signature
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F020 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
DESCRIPTION
The CAT28F020 is a high speed 256K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices.
Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
5115 FHD F02
BLOCK DIAGRAM
Doc. No. 1029, Rev. C
ALO
GEN FR
TM
LEAD FREE


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