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CAT25C08VA-1.8T3 Datasheet(Hoja de datos) 7 Page - Catalyst Semiconductor

No. de Pieza. CAT25C08VA-1.8T3
Descripción  8K/16K SPI Serial CMOS EEPROM
Descarga  16 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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7
CAT25C08/16
Doc. No. 1016, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 4. Read Instruction Timing
Note: Dashed Line= mode (1, 1) – – – –
SCK
SI
SO
0000
001
1
BYTE ADDRESS*
0123456789
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the Byte Address Table.
CS
DATA OUT
MSB
HIGH IMPEDANCE
**
AN
A0
OPCODE
bits and the WPEN bit) and the block protected sections
in the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either
WP pin is high or the
WPEN bit is zero.
DEVICE OPERATION
Write Enable and Disable
The CAT25C08/16 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes(reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling
CS low. The 8-bit read
instruction is transmitted to the CAT25C08/16, followed
by the 16-bit address for 25C08/16. (only 10-bit ad-
dresses are used for 25C08, 11-bit addresses are used
for 25C16. The rest of the bits are don't care bits).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by pulling the
CS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle.
Read
sequece is illustrated in Figure 4. Reading status register
is illustrated in Figure 5.
WRITE Sequence
The CAT25C08/16 powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25C08/16. The device goes into
Write enable state by pulling the
CS low and then
clocking the WREN instruction into CAT25C08/16. The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.




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