CAT93C66VIT3 datasheet(6/17 Pages) CATALYST

No. de pieza	CAT93C66VIT3

Descripción Electrónicos	4-Kb Microwire Serial CMOS EEPROM

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Fabricante Electrónico	CATALYST [Catalyst Semiconductor]

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CAT93C66

Doc. No. 1089 Rev. P

6

Characteristics subject to change without notice

Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the CAT93C66

will come out of the high impedance state and, after

sending an initial dummy zero bit, will begin shifting

out the data addressed (MSB first). The output data

bits will toggle on the rising edge of the SK clock and

are stable after the specified time delay (tPD0 or tPD1).

For the CAT93C66, after the initial data word has

been shifted out and CS remains asserted with the SK

clock continuing to toggle, the device will auto-

matically increment to the next address and shift out

the next data word in a sequential READ mode. As

long as CS is continuously asserted and SK continues

to toggle, the device will keep incrementing to the next

address automatically until it reaches to the end of the

address space, then loops back to address 0. In the

sequential READ mode, only the initial data word is

preceeded by a dummy zero bit. All subsequent data

words will follow without a dummy zero bit. The READ

instruction timing is illustrated in Figure 2.

Erase/Write Enable and Disable

The CAT93C66 powers up in the write disable state. Any

writing after power-up or after an EWDS (erase/write

disable) instruction must first be preceded by the EWEN

(erase/write enable)

instruction.

Once

the write

instruction is enabled, it will remain enabled until power

to the device is removed, or the EWDS instruction is

sent. The EWDS instruction can be used to disable all

CAT93C66 write and erase instructions, and will prevent

any accidental writing or clearing of the device. Data can

be read normally from the device regardless of the write

enable/disable

status.

The

EWEN

and

EWDS

instructions timing is shown in Figure 3.

Figure 1. Sychronous Data Timing

Figure 2. READ Instruction Timing

SK

CS

DI

DO

HIGH-Z

11

0

AN AN–1

A0

Dummy 0

D15 . . . D0

or

D7 . . . D0

Address + 1

D15 . . . D0

or

D7 . . . D0

Address + 2

D15 . . . D0

or

D7 . . . D0

Address + n

D15 . . .

or

D7 . . .

Don't Care

tPD0

SK

DI

CS

DO

tDIS

tPD0,tPD1

tCSMIN

tCSS

tDIS

tDIH

tSKHI

tCSH

VALID

DATA VALID

tSKLOW

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CAT93C66VIT3 Datasheet(PDF) 6 Page - Catalyst Semiconductor

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