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CAT93C66VP2IT3 Datasheet(PDF) 4 Page - Catalyst Semiconductor |
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CAT93C66VP2IT3 Datasheet(HTML) 4 Page - Catalyst Semiconductor |
4 / 17 page CAT93C66 Doc. No. 1089 Rev. P 4 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice A.C. CHARACTERISTICS (1) (NEW PRODUCT, DIE REV. G) VCC = +1.8V to +5.5V, TA = -40°C to +85°C, unless otherwise specified. Limits Symbol Parameter Min Max Units tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 µs tPD0 Output Delay to 0 0.25 µs tHZ (2) Output Delay to High-Z 100 ns tEW Program/Erase Pulse Width 5 ms tCSMIN Minimum CS Low Time 0.25 µs tSKHI Minimum SK High Time 0.25 µs tSKLOW Minimum SK Low Time 0.25 µs tSV Output Delay to Status Valid 0.25 µs SKMAX Maximum Clock Frequency DC 2000 kHz A.C. CHARACTERISTICS (1) (MATURE PRODUCT, DIE REV E – Not Recommended for New Design) Limits VCC = 1.8V - 5.5V VCC = 2.5V - 5.5V VCC = 4.5V - 5.5V Symbol Parameter Min Max Min Max Min Max Units tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 400 200 100 ns tDIH DI Hold Time 400 200 100 ns tPD1 Output Delay to 1 1 0.5 0.25 µs tPD0 Output Delay to 0 1 0.5 0.25 µs tHZ (2) Output Delay to High-Z 400 200 100 ns tEW Program/Erase Pulse Width 10 10 10 ms tCSMIN Minimum CS Low Time 1 0.5 0.25 µs tSKHI Minimum SK High Time 1 0.5 0.25 µs tSKLOW Minimum SK Low Time 1 0.5 0.25 µs tSV Output Delay to Status Valid 1 0.5 0.25 µs SKMAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz Notes : (1) Test conditions according to “A.C. Test Conditions” table. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. |
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