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CAT24WC65WA-1.8TE13D Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT24WC65WA-1.8TE13D Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 12 page Discontinued Parts CAT24WC33/65 6 Doc. No. 1049, Rev. D © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice A15–A8 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS DATA n+31 DATA A C K S T O P A C K DATA n A C K P A C K * X XX A15–A8 SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS A C K * X XX WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24WC33/65. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24WC33/65 acknowledges once more and the Master generates the STOP condi- tion. At this time, the device begins an internal program- ming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24WC33/65 writes up to 32/64 bytes of data, in a single write cycle, using the Page Write operation. CAT24WC33/65, Die Revision B = 32 Byte page. CAT24WC65, Die Revision D = 64 Byte page. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31/63 additional bytes. After each byte has been transmitted, CAT24WC33/65 will respond with an acknowledge, and internally increment the five low order address bits by one. The high order bits remain unchanged. IftheMastertransmitsmorethan32/64bytesbeforesending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 32/64 bytes are received, and the STOP condi- tion has been sent by the Master, the internal program- ming cycle begins. At this point, all received data is written to the CAT24WC33/65 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC33/65 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issu- ing the start condition followed by the slave address for a write operation. If CAT24WC33/65 is still busy with the write operation, no ACK will be returned. If CAT24WC33/65 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the bottom 1/4 of the memory array (locations 000H to 7FFH for the 24WC65 and locations 000H to 3FFH for 24WC33) is protected and becomes read only. The CAT24WC33/65 will accept both slave and byte addresses, but the memory location 24WC33/65 F09 Figure 7. Page Write Timing 24WC33/65 F08 * = Don't care bit for 24WC33 X= Don't care bit Figure 6. Byte Write Timing |
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