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CAT25C128XI-1.8-GT2 Datasheet(Hoja de datos) 5 Page - Catalyst Semiconductor

No. de Pieza. CAT25C128XI-1.8-GT2
Descripción  128K/256K-Bit SPI Serial CMOS EEPROM
Descarga  12 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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5
CAT25C128/256
Document No. 1018, Rev. I
FUNCTIONAL DESCRIPTION
The CAT25C128/256 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with
CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT25C128/256. During a read cycle, data
is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK.
CS
CS
CS
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C128/
256 and
CS high disables the CAT25C128/256. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway).
The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low transition
on
CS is required prior to any sequence being initiated. A
low to high transition on
CS after a valid write sequence is
what initiates an internal write cycle.
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
INSTRUCTION SET
Figure 1. Sychronous Data Timing
Note: Dashed Line= mode (1, 1) — — — —
VALID IN
VIH
VIL
tCSS
VIH
VIL
VIH
VIL
VOH
VOL
HI-Z
tSU
tH
tWH
tWL
tV
tCS
tCSH
tHO
tDIS
HI-Z
CS
SCK
SI
SO
tRI
tFI




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