NB6N239S datasheet(6/12 Pages) ONSEMI

No. de pieza	NB6N239S

Descripción Electrónicos	3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT 첨1/2/4/8, 첨2/4/8/16 Clock Divider

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NB6N239S

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Table 8. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 3.0 V to 3.465 V, GND = 0 V, TA = −40°C to +85°C)

Symbol

Characteristic

Min

Typ

Max

Unit

VIH

Input HIGH Voltage (LVCMOS/LVTTL)

2.0

VCC

V

VIL

Input LOW Voltage (LVCMOS/LVTTL)

GND

0.8

V

IIH

Input HIGH Current

−150

150

mA

IIL

Input LOW Current

−150

150

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

Table 9. AC CHARACTERISTICS VCC = 3.0 V to 3.465 V; GND = 0 V (Note 7)

Symbol

Characteristic

−40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

finMAX

Maximum Input CLOCK Frequency

QA/QB = (B2, B4, B8, B16)

QA = (B1)

3.0

1.5

3.0

1.5

3.0

1.5

GHz

VOUTPP Output Voltage Amplitude (Notes 9, 10)

QA(B2, 4, 8), QB(Bn)

fin v 3.0 GHz

QA(B1), QB(Bn)

fin v 1.5 GHz

200

350

450

200

350

450

200

350

450

mV

tPLH,

tPHL

Propagation Delay to

CLK, Qn

Output Differential @ 50 MHz

MR, Qn

550

420

780

660

550

420

780

660

550

420

780

660

ps

tRR

Reset Recovery

0

−90

0

−90

0

−90

ps

ts

Setup Time @ 50 MHz

EN, CLK

SELA/B, CLK

0

−60

−300

0

−60

−300

0

−60

−300

ps

th

Hold Time @ 50 MHz

CLK, EN

CLK, SELA/B

150

700

65

200

150

700

65

200

150

700

65

200

ps

tskew

Within−Device Skew @ 50 MHz

(Note 8)

Device−to−Device Skew

(Note 8)

Duty Cycle Skew

(Note 8)

5

25

30

80

40

5

30

90

45

6

30

35

90

45

ps

tPW

Minimum Pulse Width

MR

550

ps

tJITTER

RMS Random Clock Jitter

2

ps

VINPP

Input Voltage Swing (Differential Configuration)

(Note 9)

100

VCC

−GND

100

VCC

−GND

100

VCC

−GND

mV

tr

tf

Output Rise/Fall Times @ 50 MHz

Qn, Qn

(20% − 80%)

70

120

190

70

120

190

70

120

190

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

7. Measured using a 750 mV, 50% duty cycle clock source. All loading with 100 W across LVDS outputs.

8. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation

when the delays are measured from the cross point of the inputs to the cross point of the outputs.

9. Input and output voltage swing is a single−ended measurement operating in differential mode.

10.Output Voltage Amplitude (VOHCLK − VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency

divided by n, fout = fin B n. Input CLOCK frequency is v3.0 GHz.

Número de pieza similar - NB6N239S

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