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74ACT161SJ Datasheet(Hoja de datos) 6 Page - Fairchild Semiconductor

No. de Pieza. 74ACT161SJ
Descripción  Synchronous Presettable Binary Counter
Descarga  11 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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6
AC Operating Requirements for AC
Note 8: Voltage Range 3.3 is 3.3V
± 0.3V
Voltage Range 5.0 is 5.0V
± 0.5V
AC Electrical Characteristics for ACT
Note 9: Voltage Range 5.0 is 5.0V
± 0.5V
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 8)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
3.3
6.0
13.5
16
ns
Pn to CP
5.0
3.5
8.5
10.5
tH
Hold Time, HIGH or LOW
3.3
−7.0
−1
−0.5
ns
Pn to CP
5.0
−4.0
0
0
tS
Setup Time, HIGH or LOW
3.3
6.5
11.5
14
ns
PE to CP
5.0
4.0
7.5
8.5
tH
Hold Time, HIGH or LOW
3.3
−6.0
0
0
ns
PE to CP
5.0
−3.5
0.5
1
tS
Setup Time, HIGH or LOW
3.3
3.0
6.0
7
ns
CEP or CET to CP
5.0
2.0
4.5
5
tH
Hold Time, HIGH or LOW
3.3
−3.5
0
0
ns
CEP or CET to CP
5.0
−20
0.5
tW
Clock Pulse Width
3.3
2.0
3.5
4
ns
(Load) HIGH or LOW
5.0
2.0
2.5
3
tW
Clock Pulse Width
3.3
2.0
4.0
4.5
ns
(Count) HIGH or LOW
5.0
2.0
3.0
3.5
tW
MR Pulse Width,
3.3
3.0
5.5
7.5
ns
LOW
5.0
2.5
4.5
6.0
tREC
Recovery Time
−2
−0.5
0
ns
MR to CP
−10
0.5
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 9)
Min
Typ
Max
Min
Max
fMAX
Maximum Count
5.0
115
125
100
MHz
Frequency
tPLH
Propagation Delay CP to Qn
5.0
1.5
5.5
9.5
1.5
10.5
ns
(PE Input HIGH or LOW)
tPHL
Propagation Delay CP to Qn
5.0
1.5
6.0
10.5
1.5
11.5
ns
(PE Input HIGH or LOW)
tPLH
Propagation Delay
5.0
2.0
7.0
11.0
1.5
12.5
ns
CP to TC
tPHL
Propagation Delay
5.0
1.5
8.0
12.5
1.5
13.5
ns
CP to TC
tPLH
Propagation Delay
5.0
1.5
5.5
8.5
1.5
10.0
ns
CET to TC
tPHL
Propagation Delay
5.0
1.5
6.5
9.5
1.5
10.5
ns
CET to TC
tPHL
Propagation Delay
5.0
1.5
6.0
10.0
1.5
11.0
ns
MR to Qn
tPHL
Propagation Delay
5.0
2.5
8.0
13.5
2.0
14.5
ns
MR to TC




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