Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
NBSG111BAR2 Datasheet(PDF) 1 Page - ON Semiconductor |
|
NBSG111BAR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 11 page © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 8 1 Publication Order Number: NBSG111/D NBSG111 2.5V/3.3VSiGe Differential 1:10 Clock/Data Driver with RSECL* Outputs *Reduced Swing ECL Description The NBSG111 is a 1−to−10 differential clock/data driver. The device is functionally equivalent to the LVEP111 device with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors (input to VT pad) and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The Q[0:9] / Q[0:9] outputs have a differential synchronous enable (EN/EN) pin. The synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all associated specification limits are referenced to the negative edge of the selected clock input. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single−ended NECL or PECL inputs and the VMM pin is used for LVCMOS inputs. For single−ended input operation, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. Features • Maximum Input Clock Frequency > 6 GHz Typical • Maximum Input Data Rate > 6 Gb/s Typical • 300 ps Typical Propagation Delay • 60 ps Typical Rise and Fall Times • RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V • RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V • RSECL Output Level (400 mV Peak−to−Peak Output), Differential Output • 50 W Internal Input Termination Resistors • Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices • VBB and VMM Reference Voltage Output SG111 = Device Code L = Wafer Lot Y = Year W = Work Week *For further details, refer to Application Note AND8002/D FCBGA−49 BA SUFFIX CASE 489A MARKING DIAGRAM* SG 111 LYW http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ORDERING INFORMATION |
Número de pieza similar - NBSG111BAR2 |
|
Descripción similar - NBSG111BAR2 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |