NBSG16VS

http://onsemi.com

2

Figure 1. BGA−16 Pinout (Top View)

D

D

VTD

VTD

NC

Q

Q

A

B

C

D

12

3

4

Q

Q

VTD

D

D

VTD

56

7

8

16

15

14

13

12

11

10

9

1

2

3

4

NBSG16VS

Exposed Pad (EP)

Figure 2. QFN−16 Pinout (Top View)

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Description

BGA

QFN

C2

1

VTD

−

Internal 50

W Termination Pin. See Table 2.

C1

2

D

ECL, CML,

LVCMOS,

LVDS,

LVTTL

Input

Inverted Differential Input. Internal 75 k

B1

3

D

ECL, CML,

LVCMOS,

LVDS,

LVTTL

Input

Noninverted Differential Input. Internal 75 k

B2

4

VTD

−

Internal 50

W Termination Pin. See Table 2.

A1,D1,A4,

D4

5,8,13,16

−

Negative Supply Voltage

A2

6

NC

−

No Connect

A3

7

B3,C3

9,12

−

Positive Supply Voltage

B4

10

Q

RSECL

Output

Noninverted Differential Output. Typically Terminated with 50

W to

C4

11

Q

RSECL

Output

Inverted Differential Output. Typically Terminated with 50

D3

14

−

D2

15

−

ECL Reference Voltage Output

N/A

−

EP

−

Exposed Pad. (Note 2)

1. The NC pin is electrically connected to the die and must be left open.

bottom (see case drawing) must be attached to a heat−sinking conduit.

3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal

is applied then the device will be susceptible to self−oscillation.