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T89C51CC02 Datasheet(PDF) 22 Page - ATMEL Corporation |
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T89C51CC02 Datasheet(HTML) 22 Page - ATMEL Corporation |
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22 / 156 page  22 AT/T89C51CC02 4126J–CAN–05/06 Reset Recommendation to Prevent Flash Corruption When a Flash program memory is embedded on-chip, it is strongly recommended to use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys- tem malfunction during periods of insufficient power-supply voltage (power-supply failure, power supply switched off, etc.). Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 15. Entering Idle Mode T o enter Id l e m o de , s e t th e IDL bi t i n PC ON regis ter (See T abl e 16 ). T h e A/T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the A/T89C51CC02 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Exiting Idle Mode There are two ways to exit Idle mode: 1. Generate an enabled interrupt. Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe- cution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately follow- ing the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred dur- ing normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. A logic high on the RST pin clears IDL bit in PCON register directly and asynchro- nously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to address C:0000h. Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how- ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. 2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle. Power-down Mode The Power-down mode places the A/T89C51CC02 in a very low power state. Power- down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 15. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The A/T89C51CC02 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. |
Número de pieza similar - T89C51CC02_06 |
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Descripción similar - T89C51CC02_06 |
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