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T89C5115 Datasheet(PDF) 85 Page - ATMEL Corporation

No. de Pieza. T89C5115
Descripción  Low Pin Countl 8-bit Microcontroller with A/D Converter and 16 KBytes Flash Memory
Descarga  113 Pages
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Fabricante  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
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T89C5115 Datasheet(HTML) 85 Page - ATMEL Corporation

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AT89C5115
4128F–8051–05/06
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Table 60. Selected Analog input
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range (See section
“AC-DC”).
Clock Selection
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
if PRS = 0 then FADC = Fperiph / 64
if PRS > 0 then FADC = Fperiph / 2 x PRS
Figure 40. A/D Converter Clock
ADC Standby Mode
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN
in ADCON register. In this mode the power dissipation is reduced.
IT ADC management
An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit
EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.
SCH2
SCH1
SCH0
Selected Analog Input
000
AN0
001
AN1
010
AN2
011
AN3
100
AN4
101
AN5
110
AN6
111
AN7
Prescaler ADCLK
A/D
Converter
ADC Clock
CPU
CLOCK
CPU Core Clock Symbol
÷ 2


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