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T89C5115 Datasheet(PDF) 96 Page - ATMEL Corporation |
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T89C5115 Datasheet(HTML) 96 Page - ATMEL Corporation |
96 / 113 page 96 AT89C5115 4128F–8051–05/06 Table 71. IPH1 Register IPH1 (S:F7h) Interrupt high priority Register 1 Reset Value = XXXX X000b 76 54 32 1 0 - - - - - POVRH PADCH - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2POVRH Timer Overrun Interrupt Priority Level Most Significant bit POVRH POVRLPriority level 00 Lowest 01 10 1 1 Highest 1 PADCH ADC Interrupt Priority Level Most Significant bit PADCH PADCL Priority level 00 Lowest 01 10 1 1 Highest 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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