6

SY89536L

Micrel, Inc.

M9999-110405

hbwhelp@micrel.com or (408) 955-1690

V

Symbol

Parameter

Condition

Min

Typ

Max

Units

Reference Input Frequency

14

—

160

MHz

Output Frequency Range

33.33

—

500

MHz

Internal VCO Frequency Range

600

—

1000

MHz

Within Device Skew

Within Bank PECL

Note 9

——

50

ps

Within Bank HSTL

Note 9

——

75

ps

Bank-to-Bank

Note 9

—

60

150

ps

Part-to-Part Skew

Note 10

——

200

ps

Maximum PLL Lock Time

——

10

ms

Cycle-to-Cycle Jitter

(Pk-to-Pk)

Note 11

——

50

ps

Period Jitter

(rms)

Note 12

——

50

ps

Minimum Pulse Width

50

——

ps

Target PLL Loop Bandwidth

Feedback Divider Ratio: 66

Note 13

—

1.0

—

MHz

Feedback Divider Ratio: 30

Note 13

—

2.0

—

MHz

45

50

55

%

Output Rise/Fall Time

(20% to 80%)

LVPECL_Out

—

250

400

ps

HSTL_Out

100

—

400

ps

Note 14

——

10

ns

Note 14

5

——

ns

Note 14

5

——

ns

Note 14

1

——

VCO

clock cycle

FSEL-to-Valid Output Transition Time

—

50

—

ns

500

——

ps

Note 8.

All HSTL outputs loaded with 50

Ω to GND.

Note 9.

The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the

same voltage and temperature.

Note 10. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same

voltage and temperature.

Note 13. Using recommended loop filter components.

Note 14. See “Timing Diagrams."

AC ELECTRICAL CHARACTERISTICS