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CA5470E Datasheet(PDF) 5 Page - Intersil Corporation |
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CA5470E Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 5 page 5 Typical Performance Curve Metallization Mask Layout FREQUENCY 10K 14 100K 1M 10M 100M 12 10 8 6 4 2 VS = ±7.5V V+ = 5V, V- = 0V FIGURE 1. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY 97.2 (2.46) 69.7 (1.77) Dimensions in parentheses are in millimeters and derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The layout represents a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions. CA5470 |
Número de pieza similar - CA5470E |
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Descripción similar - CA5470E |
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