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SLD-1026Z Datasheet(PDF) 2 Page - SIRENZA MICRODEVICES

No. de Pieza. SLD-1026Z
Descripción  3 Watt Discrete LDMOS Device Plastic Surface Mount Package
Descarga  21 Pages
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Fabricante  SIRENZA [SIRENZA MICRODEVICES]
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SLD-1026Z Datasheet(HTML) 2 Page - SIRENZA MICRODEVICES

 
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SLD-1026Z 3 Watt LDMOS FET
303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
2
EDS-104157 Rev F
Preliminary
Quality Specifications
Parameter
Description
Rating
ESD Rating
Human Body Model
1B
DC Specifications
Symbol
Parameter
Unit
Min
Typical
Max
gm
Forward Transconductance @ 30mA IDS
mA / V
150
VGS Threshold
IDS=3mA, VDS=28V
Volts
4.2
VGS Quiescent
IDS=50mA, VDS=28V
Volts
3
4
5
VDS Breakdown
1mA VDS current
Volts
65
Ciss
Input Capacitance (Gate to Source) VGS=0V VDS=28V
pF
5.2
Crss
Reverse Capacitance (Gate to Drain) VGS=0V VDS=28V
pF
0.2
Coss
Output Capacitance (Drain to Source) VGS=0V VDS=28V
pF
3.2
RDSon
Drain to Source Resistance, VGS=10V VDS=250mV
3.0
Pin Description
Pin #
Function
Description
1, 3
NC
These pins are not connected internal to the package. Bus them to pin 2 as shown in the app circuit.
2Gate
Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant
bias current over the operating temperature range. Care must be taken to protect against video transients that exceed
the maximum input power or voltage.
4, 6
NC
These pins are not connected internal to the package. Bus them to pin 5 as shown in the app circuit.
5
Drain
Transistor RF output and drain bias voltage. Typical voltage 28V.
GND
Source, Gnd
These pins are DC connected to the backside paddle. They provide good thermal connection to the backside paddle for
hand soldering and rework. Many thermal and electrical GND vias are recommended as shown in the landing pattern.
Pin Diagram
ESD
Protection
2
GND
1
3
5
4
GND
6
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (VDS )35
Volts
Gate Voltage (VGS)20
Volts
RF Input Power
+30
dBm
Load Impedance for Continuous Operation Without Damage
10:1
VSWR
Output Device Channel Temperature
+150
ºC
Operating Temperature Range
-40 to +85
ºC
Storage Temperature Range
-40 to +150
ºC
Operation of this device beyond any one of these limits may cause permanent damage. For
reliable continuous operation see typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
Gate voltage must be applied to VGS lead concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages
should never be applied to the transistor unless it is properly terminated on both input and output.
Note 2:
The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage with LDMOS
transistors.
Note 3:
The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza
application notes AN-067 LDMOS Bias Temperature Compensation.


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