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AM29LV040B Datasheet(PDF) 12 Page - Advanced Micro Devices

No. de Pieza. AM29LV040B
Descripción  4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory
Descarga  37 Pages
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Fabricante  AMD [Advanced Micro Devices]
Página de inicio  http://www.amd.com
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AM29LV040B Datasheet(HTML) 12 Page - Advanced Micro Devices

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12
Am29LV040B
21354E4 October 11, 2006
D A TA
SH EE T
Table 3.
Am29LV040B Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection method intended only
for programming equipment requires VID on address
pin A9 and OE#. This method is compatible with pro-
grammer routines written for earlier 3.0 volt-only AMD
flash devices. Publication number 22168 contains
further details; contact an AMD representative to
request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadver tent writes (refer to Table 4 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Description
CE#
OE#
WE#
A18
to
A16
A15
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
Manufacturer ID: AMD
L
L
H
X
X
VID
XLXL
L
01h
Device ID: Am29LV040B
L
L
H
X
X
VID
XLXL
H
4Fh
Sector Protection Verification
L
L
H
SA
X
VID
XLX
H
L
01h
(protected)
00h
(unprotected)


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