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AM49PDL129BH85IS Datasheet(PDF) 7 Page - SPANSION |
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AM49PDL129BH85IS Datasheet(HTML) 7 Page - SPANSION |
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7 / 86 page  December 16, 2003 Am49PDL127BH/Am49PDL129BH 5 ADV ANCE I N FO RMAT I O N Figure 13. Timing Diagram for Alternating Between Pseudo SRAM and Flash................................................. 62 Flash AC Characteristics . . . . . . . . . . . . . . . . . . . 63 Read-Only Operations – Am29PDL127H ............................... 63 Read-Only Operations – Am29PDL129H ............................... 63 Figure 14. Read Operation Timings ................................................ 64 Figure 15. Page Read Operation Timings....................................... 64 Hardware Reset (RESET#) .................................................... 65 Figure 16. Reset Timings ................................................................ 65 Erase and Program Operations .............................................. 66 Figure 17. Program Operation Timings........................................... 67 Figure 18. Accelerated Program Timing Diagram........................... 67 Figure 19. Chip/Sector Erase Operation Timings ........................... 68 Figure 20. Back-to-back Read/Write Cycle Timings ....................... 69 Figure 21. Data# Polling Timings (During Embedded Algorithms).. 69 Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 70 Figure 23. DQ2 vs. DQ6.................................................................. 70 Temporary Sector Unprotect .................................................. 71 Figure 24. Temporary Sector Unprotect Timing Diagram ............... 71 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 72 Alternate CE#f1 Controlled Erase and Program Operations .. 73 Figure 26. Flash Alternate CE#f1 Controlled Write (Erase/Program) Operation Timings........................................................................... 74 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 75 Read Cycle ............................................................................. 75 Figure 27. Pseudo SRAM Read Cycle........................................... 75 Figure 28. Page Read Timing ........................................................ 76 Write Cycle ............................................................................. 77 Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 77 Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................ 78 Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 79 Erase And Programming Performance . . . . . . . 80 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 80 Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 80 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 80 pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . 81 pSRAM Power on and Deep Power Down . . . . . 81 Figure 32. Deep Power-down Timing............................................. 81 Figure 33. Power-on Timing........................................................... 81 pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 82 Figure 34. Read Address Skew ..................................................... 82 Figure 35. Write Address Skew...................................................... 82 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 83 TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 83 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 84 |
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