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COM20051+ Datasheet(PDF) 40 Page - SMSC Corporation |
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COM20051+ Datasheet(HTML) 40 Page - SMSC Corporation |
40 / 92 page 40 INTERNAL RAM The integration of the 1K x 8 RAM in the ARCNET core represents significant real estate savings. The PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM. The integration of RAM represents significant cost savings because it isolates the system designer from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs, and layout complexity. Sequential Access Memory The internal RAM is accessed via a pointer- based scheme. Rather than interfering with system memory, the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is channeled to and from the microcontroller via the 8-bit data register. For example: a packet in the internal RAM buffer is read by the microcontroller by writing the corresponding address into the Address Pointer High and Low Registers (offsets 02H and 03H). Note that the High Register should be written first, followed by the Low Register, because writing to the Low Register loads the address. At this point the device accesses that location and places the corresponding data into the data register. The microcontroller then reads the data register (offset 04H) to obtain the data at the specified location. If the Auto Increment bit is set to logic "1", the device will automatically increment the address and place the next byte of data into the data register, again to be read by the microcontroller. This process is continued until the entire packet is read out of RAM. Refer to Figure 12 for an illustration of the Sequential Access operation. When switching between reads and writes, the pointer must first be written with the starting address. The pointer may be read at any time to allow the microcontroller to save the present pointer value before going into a subroutine. At least one cycle time should separate the pointer being loaded and the first read (see timing parameters). Access Speed The ARCNET core is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to memory. A Slow Arbitration Bit is provided in the Setup Register to slow down the arbitration clock for buffer accesses at 5 Mbps. The SLOWARB bit must be set to a "1" for 5 Mbps operation. SOFTWARE INTERFACE The 80C32 core interfaces to the ARCNET core via software by accessing the various registers. These actions are described in the Internal Registers section. The software flow for accessing the data buffer is based on the Sequential Access scheme. The basic sequence is as follows: • Disable Interrupts • Write to Pointer Register High (specifying Auto-Increment mode.) • Write to Pointer Register Low (this loads the address.) • Enable Interrupts • Read or write the Data Register (repeat as many times as necessary to empty or fill the buffer.) |
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