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74F191 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74F191 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 12 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74F191 Rev. 1.0.2 2 Unit Loading/Fan Out Functional Description The 74F191 is a synchronous up/down 4-bit binary counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired num- ber. When the Parallel Load (PL) input is LOW, informa- tion present on the Parallel Data inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchro- nously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, pro- vided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figure 1 and Figure 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configura- tion is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only neces- sary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumula- tive delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simulta- neously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propa- gate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn’t apply, because the TC output of a given stage is not affected by its own CE. Pin Names Description U.L. HIGH / LOW Input IIH / IIL Output IOH / IOL CE Count Enable Input (Active LOW) 1.0 / 3.0 20µA / -1.8mA CP Clock Pulse Input (Active Rising Edge) 1.0 / 1.0 20µA / -0.6 mA P0–P3 Parallel Data Inputs 1.0 / 1.0 20µA / -0.6 mA PL Asynchronous Parallel Load Input (Active LOW) 1.0 / 1.0 20µA / -0.6mA U/D Up/Down Count Control Input 1.0 / 1.0 20µA / -0.6mA Q0–Q3 Flip-Flop Outputs 50 / 33.3 -1mA / 20mA RC Ripple Clock Output (Active LOW) 50 / 33.3 -1mA / 20mA TC Terminal Count Output (Active HIGH) 50 / 33.3 -1mA / 20mA |
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