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P83CL882 Datasheet(PDF) 60 Page - NXP Semiconductors |
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P83CL882 Datasheet(HTML) 60 Page - NXP Semiconductors |
60 / 88 page 2001 Jun 19 60 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 6.9.5 DATA TRANSMISSION Data transmission is enabled if bit MTEN in register MCON is set to a logic 1. If MTEN is a logic 0, data transmission is disabled and MOUT[2:0] is set to ‘111’ to zero the currents in the resistive DAC. Setting MTEN to a logic 1 sets MOUT[2:0] to the idle value ‘100’. This results in a value close to 1/2VDD on the output signal of the external DAC. Transmission is started by loading the first byte into register MBUF. All bytes are transmitted starting with the MSB. A message is transferred in a block of 3 or more bytes, the first two bytes being the programmed Manchester preamble pattern. In order to insert the preamble pattern, the first two bytes AAH and AxH (with ‘x’ being the MPR3 to MPR0 value programmed in the receiver MSK modem) have to be written to MBUF by software. After this, the first byte of the message is written to MBUF. As soon as MBUF is ready to accept new input, signal MTI is set. The minimum time between two MTI interrupts is: If no new byte is written to MBUF at the end of a byte transmission, the modem transmitter stops transmission and MOUT[2:0] is set to the idle state ‘100’. MTI must be cleared explicitly. If MTEN is reset during transmission, the transmitter will finish the transmission of the current byte and then will set MOUT[2:0] to the off state ‘111’. No interrupt on MTI will be generated at the end of the transmission. t min 8 baud rate ------------------------- = handbook, full pagewidth MGK229 MOUT 80C51 access set MTEN clear MTI write MBUF AAH write MBUF ADH write MBUF AAH write MBUF 55H write MBUF 55H MTI TX_MUTE data ADH data AAH data AAH data 55H data 55H Fig.28 Data transmission timing diagram. |
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