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P83CL781HFP Datasheet(PDF) 16 Page - NXP Semiconductors |
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P83CL781HFP Datasheet(HTML) 16 Page - NXP Semiconductors |
16 / 76 page 1997 Mar 14 16 Philips Semiconductors Product specification Low voltage 8-bit microcontrollers with UART and I2C-bus P83CL781; P83CL782 10 I/O FACILITIES 10.1 Ports The P83CL78x has 32 I/O lines treated as 32 individually addressable bits or as four parallel 8-bit ports. To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1. The alternative functions are detailed below: Port 0 Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals. Port 1 Used for a number of special functions: • Provides the inputs for the eight external interrupts: INT2 to INT9 • External activation of Timer 2: T2 • The I2C-bus interface: SCL and SDA. Port 2 Provides the high-order address when expanding the device with external Program or Data memory. Port 3 Pins can be configured individually to provide: • External interrupt request inputs: INT1 and INT0 • Timer/counter inputs: T1 and T0 • Control signals to read and write to external memories: RD and WR • UART asynchronous input and output (RXD and TXD); or UART synchronous I/O and clock lines (data and clock).1 Each port consists of a latch (SFRs P0 to P3), an output driver and input buffer. Ports 1, 2 and 3 have internal pull-ups (except P1.6 and P1.7). Figure 9(a) shows that the strong transistor ‘p1’ is turned on for only 2 oscillator periods after a LOW-to-HIGH transition in the port latch. When on, it turns on p3 (a weak pull-up) through the inverter. This inverter and p3 form a latch which holds the logic 1. In Port 0 the pull-up ‘p1’ is only on when emitting logic 1s for external memory access. Writing a logic 1 to a Port 1 bit latch leaves both output transistors switched off so that the pin can be used as an high-impedance input. 10.2 Port options 30 of the 32 port pins (excluding P1.6 and P1.7 with option 2S only) may be individually configured with one of the following options. These options are also shown in Fig.9. Option 1 Standard Port; quasi-bidirectional I/O with pull-up. The strong booster pull-up ‘p1’ is turned on for two oscillator periods after a LOW-to-HIGH transition in the port latch; Fig.9(a). Option 2 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor; Fig.9(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs; Fig.9(c). 10.3 Port 0 options The definition of port options for Port 0 is slightly different. Two cases are considered. First, access to external memory (EA = 0 or access above the built-in memory boundary) and second, I/O accesses. 10.3.1 EXTERNAL MEMORY ACCESSES Option 1 True logic 0 and logic 1 are written as address to the external memory (strong pull-up to be used). Option 2 An external pull-up resistor is required for external accesses. Option 3 Not allowed for external memory accesses as the port can only be used as output. 10.3.2 I/O ACCESSES Option 1 When writing a logic 1 to the port latch, the strong pull-up ‘p1’ will be on for 2 oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input. Option 2 Open-drain; quasi-directional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor. See Fig.9(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option pins can only be used as outputs. See Fig.9(c). 10.4 SET/RESET options Individual mask selection of the post-reset state is available with any of the above pins. The required selection is made by appending ‘S’ or ‘R’ to Options 1, 2, or 3 above. Option R RESET, at reset this pin will be initialized LOW. Option S SET, at reset this pin will be initialized HIGH. |
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