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X9523 Datasheet(PDF) 5 Page - Intersil Corporation

No. de Pieza. X9523
Descripción  Laser Diode Control for Fiber Optic Modules
Descarga  28 Pages
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Fabricante  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
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X9523 Datasheet(HTML) 5 Page - Intersil Corporation

 
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5
FN8209.1
January 3, 2006
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto-
col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9523 to
be addressed, and specifies if a Read or Write opera-
tion is to be performed.
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9523.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9523. The CON-
STAT Register may be selected using the Internal
Device Address 010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON-
STAT Register) has been correctly issued (including the
SCL
from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
8
1
9
Start
Acknowledge
Figure 3.
Acknowledge Response From Receiver
SCL
from
Master
SA6
SA7
SA5
SA3 SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ /
SA4
Internal Address
(SA3 - SA1)
Internally Addressed
Device
010
CONSTAT Register
111
DCP
All Others
RESERVED
Bit SA0
Operation
0WRITE
1
READ
R/W
Figure 4.
Slave Address Format
101 0
WRITE
ADDRESS
INTERNAL
DEVICE
X9523


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