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FM75 Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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FM75 Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 16 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FM75 Rev. 1.0.8 5 Serial Port Timing Figure 3. Serial Port Timing Diagram Symbol Parameter Conditions Min. Typ. Max. Units tSCL SCL Clock Period 1.0 100 µs tT:LH, tT:HL SCL Clock Transition Time 300 ns tLOW SCL Clock LOW Period 0.470 µs tHIGH SCL Clock HIGH Period 0.400 50 µs tBUF Bus free time between a Stop and a new Start Condition 1.0 µs tSU:DAT Data In Set-up to SCL HIGH 100 ns tHD:DAT Data In Hold Time 100 ns tHD Data Out Stable after SCL LOW 0 ns tSU:STA SCL LOW Set-up to SDA LOW (Repeated Start Condition) 100 ns tHD:STA SCL HIGH Hold after SDA LOW (Start Condition) 100 ns tSU:STO SDA HIGH after SCL HIGH (Stop Condition) 100 ns tPOR Time in which a FM75 must be operational after a power-on reset 500 ms SDA Data In tHD:STA tSCL tSU:STO tSU:DAT tHD tHD:DAT SCL SDA Data Out SCL 10% 10% 90% tT:LH tT:HL tLOW tHIGH tBUF tSU:STA 90% |
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