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ISL6116CBZA Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL6116CBZA Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 12 page 3 February 6, 2007 Simplified Block Diagram + - ISET ISEN GATE VSS VDD CTIM PGOOD PWRON CLIM WOCLIM ENABLE OC 10µA FALLING EDGE DELAY 18V + - VREF + - 1.86V 12V + - R R S QN Q ENABLE POR VDD 8V RISING EDGE PULSE + - + - UV 18V 20µA 7.5K + - + - 20µA UV DISABLE ISL611X Pin Descriptions PIN # SYMBOL FUNCTION DESCRIPTION 1 ISET Current Set Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. 2 ISEN Current Sense Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. 3 GATE External FET Gate Drive Pin Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (ISL6115) and to VDD (ISL6116, ISL6117, ISL6120) by a 10μA current source. 4 VSS Chip Return 5VDD Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. 6 CTIM Current Limit Timing Capacitor Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k Ω x C TIM. 7 PGOOD Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for the particular IC. 8 PWRON Power ON PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high to a maximum of 5V or is left open. After a current limit time out, the chip is reset by a low level signal applied to this pin. This input has 20 μA pull up capability. ISL6115, ISL6116, ISL6117, ISL6120 |
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