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TPA6130A2YZH Datasheet(PDF) 5 Page - Texas Instruments |
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TPA6130A2YZH Datasheet(HTML) 5 Page - Texas Instruments |
5 / 29 page www.ti.com ELECTRICAL CHARACTERISTICS TIMING CHARACTERISTICS (1) (2) SCL SDA tw(H) tw(L) tsu1 th1 TPA6130A2 SLOS488A – NOVEMBER 2006 – REVISED DECEMBER 2006 T A = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOS| Output offset voltage VDD = 2.5 V to 5.5 V, inputs grounded 150 400 µV PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V, inputs grounded –109 –90 dB CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V –68 dB SCL, SDA 1 |IIH| High-level input current VDD = 5.5 V, VI = VDD µA SD 10 |IIL| Low-level input current VDD = 5.5 V, VI = 0 V SCL, SDA, SD 1 µA VDD = 2.5 V to 5.5 V, SD = VDD 4 6 mA Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V 0.4 1 µA IDD Supply current SW Shutdown mode, VDD = 2.5V to 5.5 V, SWS = 1 25 75 µA Both HP amps disabled, VDD = 2.5V to 5.5 V, 1.4 2.5 mA SWS = 0, Charge Pump enabled, SD = VDD For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 µs tw(L) Pulse duration, SCL low 1.3 µs tsu1 Setup time, SDA to SCL 300 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 µs tsu2 Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tsu3 Setup time, SCL to stop condition 0.6 µs (1) VPull-up = VDD (2) A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage. Figure 1. SCL and SDA Timing 5 |
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