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TPS62353YZG Datasheet(PDF) 8 Page - Texas Instruments |
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TPS62353YZG Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 46 page  www.ti.com PIN ASSIGNMENTS TPS6235x QFN−10 (TOP VIEW) TPS6235x CSP−12 (TOP VIEW) A3 B3 C3 D3 A2 B2 C2 D2 A1 B1 C1 D1 TPS6235x CSP−12 (BOTTOM VIEW) A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 TPS62350, TPS62351 TPS62352, TPS62353, TPS62354 SLVS540B – MAY 2006 – REVISED DECEMBER 2006 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NO. NO. NAME QFN CSP PVIN 1 A3 Supply voltage for output power stage. AVIN 2 B3 This is the input voltage pin of the device. Connect directly to the input bypass capacitor. This is the enable pin of the device. Connect this pin to ground forces the device into shutdown mode. Pulling this pin to VI enables the device. On the rising edge of the enable pin, all the EN 7 C2 I registers are reset with their default values. This pin must not be left floating and must be terminated. VSEL signal is primarily used to scale the output voltage and to set the TPS6235x operation VSEL 5 D2 I between active mode (VSEL=HIGH) and sleep mode (VSEL=LOW). The mode of operation can also be adapted by I2C settings. This pin must not be left floating and must be terminated. SDA 3 C3 I/O Serial interface address/data line SCL 4 D3 I Serial interface clock line FB 6 D1 I Output feedback sense input. Connect FB to the converter output. AGND 8 C1 Analog ground Input for synchronization to external clock signal. Synchronizes the converter switching frequency SYNC N/A B2 I to an external clock signal. This pin must not be left floating and must be terminated. Connecting SYNC to static high or low state has no effect on the converter operation. PGND 9 A1 B1 Power ground. Connect to AGND underneath IC. SW 10 A2 I/O This is the switch pin of the converter and connected to the drain of the internal power MOSFETs. PowerPAD™ N/A Internally connected to PGND. 8 Submit Documentation Feedback |
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