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74VHC374 Datasheet(PDF) 1 Page - Fairchild Semiconductor

No. de pieza 74VHC374
Descripción Electrónicos  Octal D-Type Flip-Flop with 3-STATE Outputs
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Fabricante Electrónico  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74VHC374 Datasheet(HTML) 1 Page - Fairchild Semiconductor

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tm
April 2007
©1992 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC374 Rev. 1.3
74VHC374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
High Speed: tPD = 5.4ns (typ) at VCC = 5V
High noise immunity: VNIH = VNIL = 28% VCC (Min.)
Power down protection is provided on all inputs
Low power dissipation: ICC = 4µA (Max) @ TA = 25°C
Pin and function compatible with 74HC374
General Description
The VHC374 is an advanced high speed CMOS octal
flip-flop with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while main-
taining the CMOS low power dissipation. This 8-bit
D-type flip-flop is controlled by a clock input (CP) and an
output enable input (OE). When the OE input is HIGH,
the eight outputs are in a HIGH impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Order
Number
Package
Number
Package Description
74VHC374M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHC374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs


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