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ATMEGA165P_0611 Datasheet(PDF) 98 Page - ATMEL Corporation |
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ATMEGA165P_0611 Datasheet(HTML) 98 Page - ATMEL Corporation |
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98 / 368 page  98 8019H–AVR–11/06 ATmega165P 13.9.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter- rupt Flag Register – TIFR0. 13.9.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register • Bit 1 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. Bit 7654 32 1 0 (0x6E) – – – – – –OCIE0A TOIE0 TIMSK0 Read/Write RRR RRR R/W R/W Initial Value 0000 00 0 0 Bit 765 432 10 0x15 (0x35) – – – – – –OCF0A TOV0 TIFR0 Read/Write RR RRR R R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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