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MC68HC908GR8B Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc |
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MC68HC908GR8B Datasheet(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 260 page  Clock Generator Module (CGM) MC68HC908GR8B Data Sheet, Rev. 3.0 66 Freescale Semiconductor AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode 4.5.3 PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. MUL11–MUL8 — Multiplier Select Bits These read/write bits control the high byte of the modulo feedback divider that selects the VCO frequency multiplier N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NOTE The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as 0s. Address: $0038 Bit 7 654321 Bit 0 Read: 0000 MUL11 MUL10 MUL9 MUL8 Write: Reset: 00000000 = Unimplemented Figure 4-6. PLL Multiplier Select Register High (PMSH) |
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