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MC908QY2AMDWE Datasheet(PDF) 100 Page - Freescale Semiconductor, Inc

No. de pieza MC908QY2AMDWE
Descripción Electrónicos  Microcontrollers
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
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MC908QY2AMDWE Datasheet(HTML) 100 Page - Freescale Semiconductor, Inc

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Oscillator (OSC) Module
MC68HC908QYA/QTA Family Data Sheet, Rev. 2
100
Freescale Semiconductor
11.8 Registers
The oscillator module contains two registers:
Oscillator status and control register (OSCSC)
Oscillator trim register (OSCTRIM)
11.8.1 Oscillator Status and Control Register
The oscillator status and control register (OSCSC) contains the bits for switching between internal and
external clock sources. If the application uses an external crystal, bits in this register are used to select
the crystal oscillator amplifier necessary for the desired crystal. While running off the internal clock source,
the user can use bits in this register to select the internal clock source frequency.
OSCOPT1:OSCOPT0 — OSC Option Bits
These read/write bits allow the user to change the clock source for the MCU. The default reset
condition has the bus clock being derived from the internal oscillator. See 11.3.2.2 Internal to External
Clock Switching for information on changing clock sources.
ICFS1:ICFS0 — Internal Clock Frequency Select Bits
These read/write bits enable the frequency to be increased for applications requiring a faster bus clock
when running off the internal oscillator. The WAIT instruction has no effect on the oscillator logic.
BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module.
Bit 7
6
54321
Bit 0
Read:
OSCOPT1 OSCOPT0
ICFS1
ICFS0
ECFS1
ECFS0
ECGON
ECGST
Write:
Reset:
0
0
100000
= Unimplemented
Figure 11-4. Oscillator Status and Control Register (OSCSC)
OSCOPT1
OSCOPT0
Oscillator Modes
0
0
Internal oscillator (frequency selected using ICFSx bits)
0
1
External oscillator clock
10
External RC
1
1
External crystal (range selected using ECFSx bits)
ICFS1
ICFS0
Internal Clock Frequency
0
0
4.0 MHz
0
1
8.0 MHz
1
0
12.8 MHz — default reset condition
11
Reserved


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