Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD9516-2BCPZ Datasheet(PDF) 6 Page - Analog Devices |
|
AD9516-2BCPZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 84 page AD9516-2 Rev. 0 | Page 6 of 84 Parameter Min Typ Max Unit Test Conditions/Comments PLL DIGITAL LOCK DETECT WINDOW2 Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings Required to Lock (Coincidence of Edges) Selected by 0x17<1:0> and 0x18<4> Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns 0x17<1:0> = 00b, 01b,11b; 0x18<4> = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b High Range (ABP 6 ns) 3.5 ns 0x17<1:0> = 10b; 0x18<4> = 0b To Unlock After Lock (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) 7 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b High Range (ABP 6 ns) 11 ns 0x17<1:0> = 10b; 0x18<4> = 0b 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. 2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 01 1.6 GHz Distribution only (VCO divider bypassed) Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings may turn on the protection diodes and can degrade jitter performance Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Differential (OUT, OUT) Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 25 Output High Voltage (VOH) VS − 1.12 VS − 0.98 VS − 0.84 V Output Low Voltage (VOL) VS − 2.03 VS − 1.77 VS − 1.49 V Output Differential Voltage (VOD) 550 790 980 mV LVDS CLOCK OUTPUTS Differential termination 100 Ω @ 3.5 mA OUT6, OUT7, OUT8, OUT9 Differential (OUT, OUT) Output Frequency 800 MHz See Figure 26 Differential Output Voltage (VOD) 247 360 454 mV Delta VOD 25 mV Output Offset Voltage (VOS) 1.125 1.24 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND |
Número de pieza similar - AD9516-2BCPZ |
|
Descripción similar - AD9516-2BCPZ |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |