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Digital Inputs and Timing

Digital Inputs

DA[9:0]

DB[9:0]

SLEEP

CLKA/B

WRTA/B

Internal

Digital In

DVDD

DGND

GSET

MODE

Internal

Digital In

DVDD

DGND

Input Interfaces

DAC5652

SLAS452A – MARCH 2005 – REVISED FEBRUARY 2006

The data input ports of the DAC5652 accept a standard positive coding with data bits DA9 and DB9 being the

most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best

performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may

vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their

specified limits.

All digital inputs of the DAC5652 are CMOS compatible. Figure 13 and Figure 14 show schematics of the

equivalent CMOS digital inputs of the DAC5652. The 10-bit digital data input follows the offset positive binary

coding scheme. The DAC5652 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.

Figure 13. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor

Figure 14. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor

The DAC5652 features two operating modes selected by the MODE pin, as shown in Table 1.

•

For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own

separate data input bus, clock input, and data write signal (data latch-in).

•

In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The

B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.

Table 1. Operating Modes

MODE Pin

MODE pin connected to DGND

MODE pin connected to DVDD

Bus input

Single-bus interleaved mode, clock and write input equal for both DACs

Dual-bus mode, DACs operate independently

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