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AD5441 Datasheet(PDF) 3 Page - Analog Devices |
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AD5441 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 16 page  Preliminary Technical Data AD5441 Rev. PrA | Page 3 of 16 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ VDD = 5 V, VREF = 10 V, −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Condition STATIC PERFORMANCE Resolution N 12 Bits Relative Accuracy INL ±1.0 LSB Differential Nonlinearity DNL ±1.0 LSB All grades monotonic to 12 bits GFSE ±2.0 LSB Data = FFFH Gain Temperature Coefficient1 TCGFS ±5 ppm/°C IOUT pin measured Output Leakage Current ILKG ±5 nA Data = 000H, IOUT pin measured ±25 nA TA = –40°C, +125°C, Data = 000H, IOUT pin measured Zero-Scale Error IZSE 0.03 LSB Data = 000H 0.15 LSB TA = −40°C, +125°C, Data = 000H REFERENCE INPUT Input Resistance RREF 7 15 kΩ Absolute temperature coefficient < 50 ppm/°C Input Capacitance1 CREF 5 pF ANALOG OUTPUT Output Capacitance1 COUT 25 pF Data = 000H 30 pF Data = FFFH DIGITAL INPUTS Digital Input Low VIL 0.8 V Digital Input High VIH 2.4 V Input Leakage Current IIL 1 μA VLOGIC = 0 V to 5 V Input Capacitance1 CIL 10 pF VLOGIC = 0 V INTERFACE TIMING1, 2 Data Setup tDS 10 ns Data Hold tDH 5 ns Clock Width High tCH 25 ns Clock Width Low tCL 25 ns Load Pulse Width tLD 25 ns LD DAC High to MSB CLK High tLD1 0 ns LSB CLK to LD DAC tASB 0 ns AC CHARACTERISTICS1 Output Current Settling Time tS 1 μs To ±0.01% of full-scale, external op amp OP42 DAC Glitch Q 20 nVs Data = 000H to FFFH to 000H, VREF = 0 V Digital Feedthrough TBD Feedthrough (VOUT/VREF) FT 1 mV p-p VREF = 20 V p-p, data = 000H, f = 10 kHz Total Harmonic Distortion THD −85 dB VREF = 6 V rms, data = FFFH, f = 1 kHz Output Noise Density en 17 nV/√Hz 10 Hz to 100 kHz between RFB and IOUT Multiplying Bandwidth BW 2.4 MHz −3 dB, VOUT/VREF, VREF = 100 mV rms, data = FFFH Power Supply Range VDD RANGE 3 5 V Positive Supply Current IDD 10 μA VLOGIC = 0 V or VDD Power Dissipation PDISS 50 μW VLOGIC = 0 V or VDD Power Supply Sensitivity PSS 0.002 %/% ΔVDD = ±5% 1 These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. |
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