AD9865BCPZ datasheet(8/48 Pages) AD

No. de pieza	AD9865BCPZ

Descripción Electrónicos	Broadband Modem Mixed-Signal Front End

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AD9865

Rev. A | Page 8 of 48

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

Tx PATH INTERFACE (See Figure 53)

Input Nibble Rate (2× Interpolation)

Full

II

20

160

MSPS

Input Nibble Rate (4× Interpolation)

Full

II

10

100

MSPS

Tx Data Setup Time (tDS)

Full

II

2.5

ns

Tx Data Hold Time (tDH)

Full

II

1.5

ns

Rx PATH INTERFACE1 (See Figure 54)

Output Nibble Rate

Full

II

10

160

MSPS

Rx Data Valid Time (tDV)

Full

II

3

ns

Rx Data Hold Time (tDH)

Full

II

0

ns

1 CLOAD =5 pF for digital data outputs.

EXPLANATION OF TEST LEVELS

I

100% production tested.

II

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

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