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AD9995KCPRL Datasheet(PDF) 4 Page - Analog Devices

No. de pieza AD9995KCPRL
Descripción Electrónicos  12-Bit CCD Signal Processor with Precision Timing ??Generator
Download  60 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9995KCPRL Datasheet(HTML) 4 Page - Analog Devices

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AD9995
ANALOG SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Notes
CDS*
Allowable CCD Reset Transient
500
mV
Max Input Range before Saturation
1.0
V p-p
Max CCD Black Pixel Amplitude
±50
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
1024
Steps
Gain Monotonicity
Guaranteed
Gain Range
Min Gain (VGA Code 0)
6
dB
Max Gain (VGA Code 1023)
42
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
256
Steps
Clamp Level
Measured at ADC output.
Min Clamp Level (Code 0)
0
LSB
Max Clamp Level (Code 255)
255
LSB
A/D CONVERTER
Resolution
12
Bits
Differential Nonlinearity (DNL)
–1.0
±0.5
+1.0
LSB
No Missing Codes
Guaranteed
Full-Scale Input Voltage
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
V
Reference Bottom Voltage (REFB)
1.0
V
SYSTEM PERFORMANCE
Includes entire signal chain.
Gain Accuracy
Low Gain (VGA Code 0)
5.0
5.5
6.0
dB
Gain = (0.0351  Code) + 6 dB
Max Gain (VGA Code 1023)
40.5
41.5
42.5
dB
Peak Nonlinearity, 500 mV Input Signal
0.2
%
12 dB gain applied.
Total Output Noise
0.8
LSB rms
AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR)
50
dB
Measured with step change on supply.
*Input signal characteristics defined as follows:
50mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL RANGE
Specifications subject to change without notice.
(AVDD = 3.0 V, fCLI = 36 MHz, Typical Timing Specifications, TMIN to TMAX, unless otherwise noted.)
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