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NE32500N Datasheet(PDF) 1 Page - California Eastern Labs |
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NE32500N Datasheet(HTML) 1 Page - California Eastern Labs |
1 / 3 page FEATURES • SUPER LOW NOISE FIGURE: 0.45 dB TYP at 12 GHz • HIGH ASSOCIATED GAIN: 12.5 dB TYP at 12 GHz • GATE LENGTH: LG = 0.20 µ µ µ µ µm • GATE WIDTH: WG = 200 µ µ µ µ µm NEC's C TO KA BAND SUPER LOW NOISE AMPLIFIER N-CHANNEL HJ FET CHIP NE32500 DESCRIPTION NEC's NE32500 is a Hetero-Junction FET chip that uses the junction between Si-doped AlGaAs and undoped InGaAs to create very high mobility electrons. Its excellent low noise figure and high associated gain make it suitable for commercial systems and industrial applications. NEC's stringent quality assurance and test procedures assure the highest reliability and performance. PART NUMBER NE32500 PACKAGE OUTLINE 00 (Chip) SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX NF Noise Figure, VDS = 2 V, IDS = 10 mA, f = 12 GHz dB 0.45 0.55 GA Associated Gain, VDS = 2 V, IDS = 10 mA, f = 12 GHz dB 11.0 12.5 IDSS Saturated Drain Current, VDS = 2 V,VGS = 0 V mA 20 60 90 gm Transconductance, VDS = 2 V, ID = 10 mA mS 45 60 IGSO Gate to Source Leakage Current, VGS = -3 V µA 0.5 10.0 VGS(off) Gate to Source Cutoff Voltage, VDS = 2 V, ID = 100 µA V -0.2 -0.7 -2.0 RTH (CH-C) Thermal Resistance1 (Channel to Case) °C/W 260 ELECTRICAL CHARACTERISTICS (TA = 25°C) Note: 1. RF performance is determined by packaging and testing 10 chips per wafer. Wafer rejection criteria for standard devices is 2 rejects per 10 samples. California Eastern Laboratories OUTLINE DIMENSIONS (Units in µm) CHIP 49.5 43 25 13 76.5 350 100.5 89 25 21 13 25 5.5 36.5 13 25 66 58 38 68 60 46.5 350 Source Source Drain Gate 66 Thickness = 140 µm Bonding Area |
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