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MC9S12XHZ512 Datasheet(PDF) 55 Page - Freescale Semiconductor, Inc |
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MC9S12XHZ512 Datasheet(HTML) 55 Page - Freescale Semiconductor, Inc |
55 / 1016 page Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 55 1.5.2.4 System Wait Mode This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in system wait mode. For further power consumption savings, the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that has not been masked ends system wait mode. 1.5.3 Freeze Mode The enhanced capture timer, pulse width modulator, analog-to-digital converter, the periodic interrupt timer and the XGATE module provide a software programmable option to freeze the module status during the background debug module is active. This is useful when debugging application software. For detailed description of the behavior of the ATD, ECT, PWM, XGATE and PIT when the background debug module is active consult the corresponding module block description chapters. 1.6 Resets and Interrupts Consult the S12XCPU block description chapter for information on exception processing. 1.6.1 Vectors Table 1-9 lists all interrupt sources and vectors in the default order of priority. The interrupt module (S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each I-bit maskable service request is a configuration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module. |
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