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MC33991DWR2 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MC33991DWR2 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 36 page Analog Integrated Circuit Device Data 10 Freescale Semiconductor 33991 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS SPI TIMING INTERFACE Recommended Frequency of SPI Operation fSPI — 1.0 3.0 MHz Falling edge of CS to Rising Edge of SCLK (Required Setup Time)(15) TLEAD — 50 167 ns Falling edge of SCLK to Rising Edge of CS (Required Setup Time) (15) TLAG — 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (15) TSLSU — 25 83 ns Falling Edge of SCLK to SI (Required Hold Time) (15) TSI(HOLD) — 25 83 ns SO Rise Time (CL=200pF) TrSO — 25 50 ns SO Fall Time (CL=200pF) TfSO — 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time (16) TrSI — — 50 ns SI, CS, SCLK, Incoming Signal Fall Time (16) TfSI — — 50 ns Falling Edge of RST to Rising Edge of RST (Required Setup Time)(15) TwRST — — 3.0 µs 14. Rising Edge of CS to Falling Edge of CS (Required Setup Time)(15) (20) T CS — — 5.0 µs Rising Edge of RST to Falling Edge of CS (Required Setup Time)(15) TEN — — 5.0 µs Time from Falling Edge of CS to SO Low Impedance (17) TSO(EN) — — 145 ns Time from Rising Edge of CS to SO High Impedance (18) TSO(DIS) — 1.3 4.0 µs Time from Rising Edge of SCLK to SO Data Valid (19) 0.2 VDD < = SO> = 0.8 VDD, CL = 200 pF TVALID — 65 105 ns Notes 15. The maximum setup time that is specified for the 33991 is the minimum time needed from the micro controller to guarantee correct operation. 16. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 17. Time required for output status data to be available for use at SO. 1 K Ohm load on SO 18. Time required for output status data to be terminated at SO. 1 K Ohm load on SO. 19. Time required to obtain valid data out from SO following the rise of SCLK. 20. This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes. The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing, over the temperature range specified in the environmental requirements section. Digital Interface timing is based on a symmetrical 50% duty cycle SCLK Clock Period of 333 ns. The device shall be fully functional for slower clock speeds. Table 3. Static Electrical Characteristics (continued) (Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit |
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